1. Field of the Invention
The present invention relates to integrated circuits, and more particularly, to scan testing of integrated circuits.
2. Background of Invention
Effective testing of integrated circuits significantly enhances the ability of integrated circuit developers and manufacturers to provide reliable devices. Various techniques have been employed to test integrated circuits during the manufacturing process. One such technique that is commonly known, and has been used within the industry for over twenty years is scan testing.
Scan testing provides an efficient approach to testing the structural integrity of devices, such as flip-flops, within a complex integrated circuit. Scan testing does not test integrated circuit-level functionality. Rather, test personnel use scan testing to confirm that individual flip-flops within an integrated circuit function properly. The sheer number of flip-flops within an integrated circuit, which is often greater than a million, presents a daunting challenge for testing. Scan testing addresses this challenge through the use of automated test units that provide test vectors to scan paths including thousands of flip-flops within integrated circuits that have been designed to support scan testing.
Typically, complex integrated circuits are designed and implemented as a series of interconnected functional blocks, each of which can be tested independently. Devices, such as flip-flops, within these functional blocks can be designed, such that they can be connected together in a scan path to support scan testing. Flip-flops and other elements within a scan path include, in addition to inputs and outputs used for normal operation, two inputs associated with the scan testing capability. These include a scan input (SI) and a scan enable (SE) input. Flip-flops within a scan path have their output connected to the SI input of a subsequent flip-flop. The first flip-flop within a scan path receives its input from an automated test unit through a test access port on the chip. The last flip-flop within a scan path provides its output to the automated test unit through a test access port. Many scan paths can exist within a single integrated circuit.
While scan testing provides significant benefits, a shortcoming exists related to efficiently debugging a scan testing failure to identify the source or sources of the failure. Identifying the source of a scan path failure can be quite difficult. A typical integrated circuit can include many scan paths with each scan path including as many as 10,000 flip-flops. Furthermore, when there is a failure point within a particular scan path, errors will be generated on the output of that scan path, but also can be propagated to other scan paths through logical and physical interconnections. Thus, scan paths that are good (i.e., do not have failure points within their path) can also generate unexpected results.
A wide variety of sources for errors can exist. For example, errors can be caused by a bad layout of the integrated circuit in which the circuit can function normally at a particularly frequency, temperature or voltage, but when these factors are changed errors can occur. In another example, a bad design, such as using a latch instead of a flip-flop, can cause errors. Yet another example, could be that the mask used to fabricate the integrated circuit was defective leading to broken connections between flip-flops or poorly performing flip-flops. Finally, a wrong wiring diagram can be used by the tester. In this case, a tester might perceive errors, which are not actually errors. Given the large number of scan paths, the large number of flip-flops in a scan path, the interrelationship between scan paths and the many possible sources of errors debugging scan test failures can take days or even months.
What is needed is a method for efficiently debugging scan testing failures to identify the source of the failure.